The present invention relates generally to the field of imaging, and in particular to semiconductor imaging devices and methods of producing such devices.
A variety of semiconductor imaging devices are known in the art. Such devices typically comprise semiconductor material such as cadmium telluride (CdTe), cadmium zinc telluride (CdZnTe), mercury iodide (HgI2), indium antimonide (InSb), gallium arsenide (GaAs), geranium (Ge), titanium bromide (TiBr), lead iodide (PbI) and silicon (Si). For example, an imaging pixel semiconductor system is disclosed in published International Patent Application WO-A-95/33332 owned by the assignee hereof. The contents of that document are incorporated herein by reference.
Known silicon-based semiconductor imaging devices have been implemented with a continuous grounded metal guard ring or pattern in electrical contact with the semiconductor material and encompassing the pixel contacts. The guard ring is formed on the sensitive face of the semiconductor material in the pixel plane adjacent to the edge of the material. The guard ring can improve electric field uniformity at the edge of the material which might otherwise cause image deterioration.
In such devices, however, the guard ring occupies a significant area of the sensitive surface, creating a substantial xe2x80x9cinactivexe2x80x9d area around the periphery of the detector face. The region is inactive in the sense that it is extremely difficult or impossible to detect photons incident in this region, since any charge created by absorption of photons flows immediately to ground via the grounded guard ring. Typically, the pixel pitch might be as small as 35 xcexcm, and the width of the guard ring might be at least as big, if not significantly bigger (typically the width is in the range 25-500 xcexcm). The inactive area causes particular problems when several individual detectors are used together to form a tiled detector surface. The combined effect of the guard rings of adjacent tiles can create a blind area of 1 mm or more in width at the region of the tile edges. Such a blind area is unacceptable for high-sensitivity or high-resolution imaging.
Embodiments of the present invention are directed to solving these and other problems with known imaging devices.
According to embodiments of the present invention, edge deterioration effects in a semiconductor imaging device may be reduced or substantially eliminated by arranging an edge-most contact element or elements on the surface of the semiconductor material sufficiently close to the edge of the material. In one such embodiment, the distance between the edge of at least one charge collecting contact of a semiconductor imaging device and the edge of the semiconductor material is between 0 and about 500 xcexcm and/or between 0 and a value not significantly greater than ⅓ of the thickness of the semiconductor material.
By arranging at least some of the edge-most contacts close to the edge of the semiconductor material, the field non-uniformities may be displaced closer to the edge of the semiconductor material and, if the spacing is sufficiently small, extend at least partly beyond (i.e., outside) the semiconductor volume. It will be appreciated that a reduction in the size of the semiconductor region affected by the non-uniformities will achieve a corresponding reduction in Image Deterioration Effect (IDE) at the edge of the detector.
The spacing between the edge of the semiconductor material and the outermost edge or edges of the (or each) pixel contact may be made sufficiently small to reduce or alleviate IDE in the detector when in use. Generally, best results are achieved if the spacing is made as small as possible.
Applying the teachings of the present invention, suitable spacing for any particular semiconductor detector can be found by routine investigation, such as by routine experimentation or by simulation of the electrostatic fields as described herein. For example, in accordance with embodiments of the present invention, the spacing may be configured not significantly greater than about ⅕, or about {fraction (1/15)}, or about {fraction (1/30)}, or about {fraction (1/50)}, of the semiconductor thickness (with increasing preference for smaller fractions). Such ratios of spacing/thickness can provide increasingly better results in alleviating edge IDE. Likewise, the edge spacing may be configured not significantly greater than about 300 xcexcm, or 100 xcexcm, or 50 xcexcm or 30 xcexcm (with increasing preference for smaller values). These values match the above fractions for a semiconductor thickness of 1.5 mm, but can also be applied irrespective of the semiconductor thickness in other cases. In still other embodiments, selected ones of the foregoing values may also be combined to give a preferred spacing of not significantly greater than about ⅓ (or ⅕, etc.) of the semiconductor thickness if greater than 1.5 mm, and not significantly greater than about 500 xcexcm (or 300 xcexcm, etc.) if the semiconductor thickness is generally equal to or less than 1.5 mm.
Various methods can be used to produce semiconductor imaging devices having an edge spacing as described above. According to one embodiment of such a method, the contact(s) are formed on the surface of a pre-cut (or pre-formed) semiconductor substrate of a desired size using photolithography. Modern photolithographic techniques can be used to form a contact within about 50 xcexcm of the substrate edge. According to another embodiment, the contact(s) may be formed on the surface of an oversized substrate using any convenient technique, and the edge of the substrate then cut close to the edge-most contact(s). Modern cutting techniques can be used to form a cut to a precision of about 10 xcexcm or better.
According to yet another embodiment, an edge-most portion of at least one charge collecting contact of a semiconductor imaging device is spaced from the surface of the semiconductor material by passivation material. For example, the edge-most contacts may have a step profile (or at least the side of the contact adjacent to the semiconductor material may have a step profile) and be arranged so that the portion which steps away from the surface of the semiconductor substrate extends towards the edge of the semiconductor substrate. This takes into account that strong field non-uniformities are believed only to exist in the semiconductor material very close to the surface on which the charge collection contacts are mounted. By spacing the edge-most portion of the contact from the semiconductor surface, and introducing a passivation layer, the most intense field is confined to the non-sensitive passivation material where no breakdown effect is possible. Such a technique may be particularly effective when used in combination with the previously-discussed technique of positioning the edge-most charge collection contact(s) close to the edge of the semiconductor material.
In yet another embodiment, a non-sensitive field shaping region may be arranged outside, but adjacent to, at least one edge of the semiconductor imaging device. Such an arrangement can avoid reducing the area on which charge collection contacts can be mounted (which is a deficiency of using a guard ring), yet still provide a field shaping or controlling effect to reduce edge IDE problems. For example, the field shaping region may comprise non-sensitive material within which is or are arranged one or more field shaping strips. The positions of the strips, and the potential(s) applied to the strips can be chosen to achieve the desired field shaping. Different potentials can be applied to different strips if desired. The field shaping region may extend around the periphery of each single detector element. Additionally, or alternatively, the field shaping region may extend around the external periphery of a detector made up of a number of separate detector units (e.g., tiles) positioned side-by-side.
According to another embodiment of the present invention, two or more detector units may be arranged in very close proximity with each other, or in direct contact with each other. Typically, the detectors may be arranged with a gap of not significantly more than 500 xcexcm. With increasing preference for smaller gaps, the spacing is more preferably not significantly greater than about 300 xcexcm, or about 100 xcexcm, or about 50 xcexcm or less (which is equivalent to direct contact). With such close xe2x80x9cspacing,xe2x80x9d the strong edge field non-uniformities of one detector may at least partially cancel out the corresponding edge non-uniformities of an adjacent detector, and thereby reduce the likelihood of edge IDE. This proximity of neighboring tiles on an imaging support plane is feasible with existing positioning and aligning methods. Such a technique may be most effective when used in combination with the technique of positioning the edge-most charge collection contact(s) very close to the edge of the semiconductor material and/or in combination with the technique of using passivation between an edge-most portion of a contact and the semiconductor material.
In yet another embodiment, a window region may be defined on the radiation receiving surface of a semiconductor imaging device, or of an arrangement of several devices, for receiving incident radiation. The window region would be smaller than the overall surface of the device or devices. Accordingly, one or more regions of the surface are shielded from receiving incident radiation. With such a technique, incident radiation can be confined to a region of the semiconductor material where strong field non-uniformities are absent. Preferably, at least one edge region of the substrate is shielded to prevent charge being produced in the edge region vulnerable to IDE. One feature of IDE is that once a charge avalanche has started, the avalanche affects not only the closest charge collecting contact, but also spreads to affect other contacts in the vicinity. By reducing the xe2x80x9cwindowxe2x80x9d of the detector even by a modest amount to reduce the amount of incident radiation in regions of strong field non-uniformity, and thereby suppress IDE, a significant improvement may be achieved. In one form, the window region may correspond to the area in alignment with the charge collecting contacts formed on the opposite surface of the semiconductor material. Alternatively, the window region may be slightly smaller than this, so that some of the edge-most contacts are in the shielded region.
In accordance with another embodiment, at least a portion of a field shaping conductor adjacent to the surface of the semiconductor material of a semiconductor imaging device is spaced from the surface by passivation material. Preferably, the conductor is insulated electrically from the semiconductive material by the passivation material. Therefore, in contrast to known approaches, a field shaping, or xe2x80x9cguard,xe2x80x9d conductor should not make electrical contact with the surface of the semiconductor material. By electrically isolating the field shaping conductor from the semiconductor material, charge created by incident photons cannot flow out through the conductor. Instead, the charge is available to flow towards an adjacent charge collection contact, as a detectable output. The proximity of the conductor to the semiconductor material nevertheless enables it to provide a field shaping, or xe2x80x9cguard,xe2x80x9d effect to reduce field non-uniformities at the edge of the semiconductor material. The conductor may be coupled to ground, or to some other potential, for this purpose.
With the above arrangement using the field shaping conductor, the sensitivity of the detector in the edge regions can thus be improved, but the presence of the guard ring may limit the resolution in the edge region of the detector. It is preferred that the width of the guard conductor on the semiconductor surface be not significantly greater than about 100 xcexcm, so that it does not occupy too much surface area. With a guard conductor of this width, the xe2x80x9cholexe2x80x9d in the resolution at the detector edge is also about 100 xcexcm.
The foregoing embodiments and/or features thereof may be used independently or in combination. In contrast to the teaching of the prior art, the above aspects can enable incident radiation to be detected in the peripheral region of the semiconductive material. This provides an extremely important advantage in improving the sensitivity of the detector in the edge regions, and can enable the size of xe2x80x9cdeadxe2x80x9d or xe2x80x9cblindxe2x80x9d regions of the detector to be reduced compared to currently known devices. According to embodiments of the present invention, two or more detectors can be arranged in a one-, two- or three-dimensional pattern (such as a tiled detector surface) and can provide a much more uniform sensitivity across the entire width of the detection surface than is possible with current technology. Moreover, embodiments of the present invention can reduce or even alleviate field non-uniformities at the edge of the detector sensitive area while, at the same time, achieving a sensitive area which is maximal and substantially equal to the total area of the detector.